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Rev 0; 1/06
Dual NV Audio Taper Digital Potentiometer
General Description
The DS1881 is a dual, nonvolatile (NV) digital potentiometer designed to operate in audio systems that require 5V signal levels. The potentiometer settings can be stored in EEPROM so that they are retained when the power is cycled. The DS1881 has separate supplies for the potentiometers (VCC) and the communication circuitry (VDD). For clickless/popless operation, a zero-crossing detector allows the wiper position to change when there is no voltage across the potentiometer. The device is also designed to minimize crosstalk, and the two digital potentiometers provide 0.5dB channel-to-channel matching to prevent volume differences between channels. Total harmonic distortion (THD) is also minimal as long as the wiper drives a high-impedance load. Two attenuation configuration options provide optimum flexibility for the specific application. Configuration Option 1 provides 63 logarithmic tapered steps (0dB to -62dB, 1dB/step) plus a mute setting. Configuration Option 2 has 32 logarithmic steps plus mute and provides software compatibility with the DS1808. When Configuration Option 2 is used in combination with the 16-pin SO package, the DS1881 is both software and pin compatible with the DS1808 in 5V applications.
Features
Dual, Audio Log Taper Potentiometers Low THD+N and Crosstalk 5V Analog Supply (Independent of Digital Supply) 3V to 5V Digital Supply Range Potentiometer Settings Configurable as NV or Volatile Zero-Crossing Detector Eliminates Switching Noise Two User-Configurable Attenuation Options Configuration Option 1: 63 Positions Provide 1dB Attenuation Steps from 0dB to -62dB Plus Mute Configuration Option 2: (Software-Compatible with the DS1808): 33 Positions Plus Mute as Follows Positions 0-12: 1dB per Step for 12 Steps Positions 13-24: 2dB per Step for 12 Steps Positions 25-32: 3dB per Step for 8 Steps I2C*-Compatible Serial Interface Three Address Pins Allow Up to 8 Devices on I2C Bus 45k Potentiometer End-to-End Resistance Industrial Temperature Range (-40C to +85C) 16-Pin TSSOP or SO Package
DS1881

Applications
Notebook and PC Audio Portable Audio Equipment Car Stereo Consumer Audio/Video
Ordering Information
PART DS1881E-045+
Pin Configuration
TOP VIEW
GND 1 A2 2 A1 3 N.C. 4 A0 5 W0 6 L0 7 H0 8
TEMP RANGE -40C to +85C
VERSION PIN(k) PACKAGE 45 16 TSSOP (173 mils) 16 TSSOP (173 mils) Tape-and-Reel 16 SO (150 mils) 16 SO (150 mils) Tape-and-Reel
+
16 VDD 15 VCC 14 SCL
DS1881E-045+T&R -40C to +85C
45
DS1881
13 SDA 12 CE 11 W1 10 H1 9 L1
DS1881Z-045+
-40C to +85C
45
DS1881Z-045+T&R -40C to +85C
45
+Denotes lead-free package.
TSSOP/SO Typical Operating Circuit appears at end of data sheet. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual NV Audio Taper Digital Potentiometer DS1881
ABSOLUTE MAXIMUM RATINGS
Voltage on VDD, SDA, and SCL Relative to GND .....-0.5V to +6.0V Voltage on A2, A1, A0, and CE Relative to GND .................-0.5V to (VDD + 0.5V), not to exceed +6.0V Voltage on VCC Relative to GND ...........................-0.5V to +6.0V Voltage on H1, H0, W1, W0, L1, and L0 Relative to GND...............................................................-0.5V to +6.0V Maximum Resistor Current .................................................3mA Operating Temperature Range ...........................-40C to +85C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Digital Supply Voltage Analog Supply Range Potentiometer Voltages Wiper Current SYMBOL VDD VCC CONDITIONS (Notes 1, 2) (Notes 1, 2) MIN 2.7 4.5 0 TYP MAX 5.5 5.5 5.5 1 UNITS V V V mA
DC ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, VCC = +4.5V to +5.5V, TA = -40C to +85C.)
PARAMETER Digital Supply Current Analog Supply Current Input Logic 0 (CE, SDA, SCL, A0, A1, A2) Input Logic 1 (CE, SDA, SCL, A0, A1, A2) Output-Voltage Low (SDA) Input Leakage Current I/O Pin Input Current (SDA) I/O Capacitance Power-Up Time CI/O tPU SYMBOL IDD ICC VIL VIH VOL ILI 0.4V < VSDA < (0.9 x VCC) (Note 6) (Note 3) (Note 4) (Note 5) (Note 5) IOL = 4mA IOL = 6mA -1 -10 -0.3 0.7 x VDD CONDITIONS MIN TYP 200 0.9 MAX 250 5 0.3x VDD VDD + 0.3 0.4 0.6 +1 +10 10 1 UNITS A A V V V A A pF ms
2
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Dual NV Audio Taper Digital Potentiometer
ANALOG POTENTIOMETER CHARACTERISTICS
(VDD = +2.7V to +5.5V, VCC = +4.5V to +5.5V, TA = -40C to +85C.)
PARAMETER End-to-End Resistance End-to-End Resistance Tolerance Ratiometric Temperature Coefficient End-to-End Resistance Temperature Coefficient Wiper Resistance Absolute Attenuation Tolerance Mute Position Attenuation Step Size Deviation from Nominal Interchannel Matching -3dB Cutoff Frequency Output Noise Crosstalk THD+N Zero-Crossing Detection tZCD (Note 7) (Note 7) 10pF load (20Hz to 20kHz, grounded input, tap = -6dB) (1kHz, grounded input, tap = -6dB) 1kHz, tap = -6dB, CL = 10pF (Note 8) -0.25 -0.5 5 2.2 -110 0.005 38 50 RW (Note 7) -0.5 80 +0.25 +0.5 SYMBOL REE +25C +25C (Note 6) (Note 6) -20 30 750 160 250 +0.5 CONDITIONS MIN TYP 45 +20 MAX UNITS k % ppm/C ppm/C dB dB dB dB MHz VRMS dB % ms
DS1881
I2C CHARACTERISTICS (See Figure 4)
(VDD = +2.7V to +5.5V, VCC = +4.5V to +5.5V, TA = -40C to +85C. Timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW (Note 10) (Note 11) 5 (Note 10) (Note 10) (Note 9) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 10 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
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Dual NV Audio Taper Digital Potentiometer DS1881
NV MEMORY CHARACTERISTICS
(VDD = +2.7V to +5.5V, VCC = +4.5V to +5.5V, TA = 0C to +70C.)
PARAMETER Writes SYMBOL CONDITIONS +70C (Note 6) MIN 50,000 TYP MAX UNITS
All voltages are referenced to ground. The value of VDD should never exceed VCC, including during power-ups. VCC must be applied before VDD. IDD is specified with SDA = SCL = CE = VDD, resistor pins floating, and digital inputs connected to VDD or GND. ICC is specified with SDA = SCL = CE = VDD, resistor pins floating, and digital inputs connected to VDD or GND, after zerocrossing detection has timed out. Note 5: The DS1881 will not obstruct the SDA and SCL lines if VDD is switched off as long as the voltages applied to these inputs do not violate their minimum and maximum input voltage levels. Note 6: Guaranteed by design. Note 7: Above Position 50, these are typical maximum. Guaranteed by characterization. Note 8: Load is representative of the input of a low-noise audio amp. Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing. Note 10: CB--Total capacitance of one bus line in picofarads. Note 11: If zero-crossing detection is enabled, the EEPROM write does not begin until the current zero-crossing detection is complete. Otherwise, EEPROM write begins after a STOP condition occurs. Note 1: Note 2: Note 3: Note 4:
Typical Operating Characteristics
(VDD = VCC = +5.0V, TA = +25C.)
IDD vs. VDD
DS1881 toc01
IDD vs. TEMPERATURE
DS1881 toc02
IDD vs. SCL FREQUENCY
SDA = VDD 350 ACTIVE SUPPLY CURRENT (A) 300 250 200 150 100 50 0
DS1881 toc03
300 280 260 SUPPLY CURRENT (A) 240 220 200 180 160 140 120 100 4.5 4.7 4.9 5.1 5.3 SDA = SCL = VCC
400 SDA = SCL = VDD 350 SUPPLY CURRENT (A) 300 250 200 150 100 50 0
400
5.5
-40
-20
0
20
40
60
80
0
50
100 150 200 250 300 350 400 SCL FREQUENCY (kHz)
VOLTAGE (V)
TEMPERATURE (C)
4
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Dual NV Audio Taper Digital Potentiometer DS1881
Typical Operating Characteristics (continued)
(VDD = VCC = +5.0V, TA = +25C.)
POTENTIOMETER 0 (CONFIGURATON 1) ATTENUATION vs. SETTING
DS1881 toc04
POTENTIOMETER 0 (CONFIGURATON 2) ATTENUATION vs. SETTING
DS1881 toc05
POTENTIOMETER 1 (CONFIGURATON 1) ATTENUATION vs. SETTING
DS1881 toc06
0
0
0
-20.0 ATTENUATION (dB)
-20.0 ATTENUATION (dB)
-20.0 ATTENUATION (dB)
-40.0
-40.0
-40.0
-60.0
-60.0
-60.0
-80.0
-80.0
-80.0
-100.0 0 9 18 27 36 45 54 63 SETTING (DEC)
-100.0 0 3 6 9 12 15 18 21 24 27 30 33 SETTING (DEC)
-100.0 0 9 18 27 36 45 54 63 SETTING (DEC)
DS1881 toc07
RESISTANCE % CHANGE (FROM +25C)
DS1881 toc08
0
RESISTANCE (k)
-20.0 ATTENUATION (dB)
-40.0
-60.0
-80.0
-100.0 0 3 6 9 12 15 18 21 24 27 30 33 SETTING (DEC)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
HIGH IMPEDANCE 80
60
40 MUTE WHILE EEPROM LOADS
PROGRAMMED RESISTANCE (-6dB)
POTENTIOMETER 1 POTENTIOMETER 0
20
0 0 1 2 3 4 5 80 POWER-UP VOLTAGE (V)
-40
-20
0
20
40
60
TEMPERATURE (C)
RESISTANCE vs. POWER-DOWN VOLTAGE
DS1881 toc10
SUPPLY CURRENT vs. ZERO-CROSSING TIMING
900 800 700 ICC (A) ZERO-CROSSING DETECTION ACTIVATED ZERO-CROSSING TIMEOUT OR ZEROCROSSING EVENT
DS1881 toc11
100
1000
80 RESISTANCE (k)
60
600 500 400 300 200 100
40
PROGRAMMED RESISTANCE (-6dB) MUTE
20
TYPICAL TIMEOUT OF 50ms TIME (ms)
0 0 1 2 3 4 5 POWER-UP VOLTAGE (V)
0
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DS1881 toc09
POTENTIOMETER 1 (CONFIGURATON 2) ATTENUATION vs. SETTING
END-TO-END RESISTANCE PERCENT CHANGE FROM +25C vs. TEMPERATURE
RESISTANCE vs. POWER-UP VOLTAGE
100
5
Dual NV Audio Taper Digital Potentiometer DS1881
Typical Operating Characteristics (continued)
(VDD = VCC = +5.0V, TA = +25C.) THD+N vs. FREQUENCY (0dB)
DS1881 toc12
CROSSTALK vs. FREQUENCY (-6dB)
DS1881 toc13
0.0018 0.0016 0.0014 0.0012 THD+N (%) 0.0010 0.0008 0.0006 0.0004 0.0002 0 0.01 0.1 1 FREQUENCY (kHz) 10
0 -20 CROSSTALK (dB) -40 -60 -80 -100 -120 -140
100
0.01
0.1
1 FREQUENCY (kHz)
10
100
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME GND A2 A1 N.C. A0 W0 L0 H0 L1 H1 W1 CE SDA SCL VCC VDD Ground I2C Address Inputs. Inputs A0, A1, and A2 determine the I2C slave address of the device. No Connection I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. Wiper Terminal for Potentiometer 0 Low Terminal for Potentiometer 0 High Terminal for Potentiometer 0 Low Terminal for Potentiometer 1 High Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Chip Enable. Enables SDA and SCL pins for I2C communication. I2C Serial-Data Open-Drain I/O I2C Serial-Clock Input Analog Voltage Supply Digital Voltage Supply FUNCTION
6
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Dual NV Audio Taper Digital Potentiometer
Block Diagram
DS1881
SDA SCL A2 A1 A0 CE
VDD CONFIGURATION REGISTER I2C INTERFACE POTENTIOMETER SETTING REGISTERS
VCC VCC VDD GND
DS1881
GND
POTENTIOMETER 0 VALUE H0 W0 L0 ZERO-CROSSING DETECTOR
DECODER
POTENTIOMETER 1 VALUE H1 W1 ZERO-CROSSING DETECTOR L1
UPDATE
UPDATE
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Dual NV Audio Taper Digital Potentiometer DS1881
Detailed Description
The DS1881 is a dual-channel, digitally controlled, audio potentiometer. The Block Diagram illustrates the features of the DS1881. The following sections discuss these features in detail.
Table 1. Configuration Option 1
TAP POSITION 0 1 2 3 4 5 6 7 8 ... 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 ATTENUATION (dB) 0 1 2 3 4 5 6 7 8 ... 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 80
Potentiometer Configurations
The DS1881 potentiometers have two possible attenuation configuration options. The Configuration Register section discusses how to change between the two options. Note that both potentiometers are always set to the same option. The factory default for both potentiometers is Option 1 (see Table 1). Option 1 provides 64 positions with 1dB attenuation per step for positions 0 through 62 and mute as position 63. Option 2 (see Table 2) is a 34position configuration. From position 0, the first 12 steps have 1dB attenuation per step, the next 12 have 2dB attenuation per step, and the following 8 steps have 3dB attenuation per step. The last position, position 33, is the mute setting.
Zero-Crossing Detection
Zero-crossing detection is a user-selectable feature used to help eliminate clicking or popping noises during changes of potentiometer settings. See the Configuration Register section to learn how to enable the zero-crossing detection feature. After the I2C master issues a command to change the wiper position and the DS1881 has responded with an acknowledge (ACK) to the command, the DS1881 has a 50ms window to change the wiper position. The DS1881 constantly monitors the voltage of the high and low terminals of both potentiometers. During the 50ms window, if the zero-crossing detection is enabled, then each potentiometer's wiper will change position if the high and low terminals of the same potentiometer become equal in potential (i.e., the magnitude of the input signal is zero). If a zero-crossing event does not occur within the 50ms window, then the wiper is allowed to change to the new position regardless of the state of the input signal. When the zero-crossing detection feature is not enabled, the DS1881 will allow wiper movement as soon as the DS1881 has issued the acknowledge to the master-controlling device.
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Dual NV Audio Taper Digital Potentiometer
Table 2. Configuration Option 2
TAP POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ATTENUATION (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 14 16 18 20 22 24 26 28 30 32 34 36 39 42 45 48 51 54 57 60 80
MSB LSB CONFIGURATION SELECTION REGISTER SETTINGS
Command Byte
The Command Byte determines both the potentiometer wiper settings and the configuration of both potentiometers. This is done by setting the two MSBs of the Command Byte to one of three values. If 00 is set as the value for the two MSBs, then the wiper setting for Potentiometer 0 is to be programmed. If 01 is set as the value, then the wiper setting of Potentiometer 1 is to be programmed. See the Potentiometer Wiper Setting section for more details about writing the wiper setting. A value of 10 indicates that the Configuration Register is to be programmed. A value of 11 is reserved and is not to be used. See the Configuration Register section for more information. Any values other than the three discussed above will result in no action by the part. See below for the Command Byte structure.
DS1881
Command Byte Structure
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Dual NV Audio Taper Digital Potentiometer DS1881
Potentiometer Wiper Setting If 00 or 01 are the values of the two MSBs of the Command Byte, then the wiper settings of the potentiometers are to be programmed. The lower 6 LSBs of the Command Byte are then used to store the wiper settings for the selected potentiometer. See below for the potentiometer wiper setting details.
POTENTIOMETER WIPER REGISTER
Factory Default: Memory Type: XX111111b NV (EEPROM)
0 b7
X b6 b5 b4
WIPER SETTING b3 b2 b1 b0
bits 7, 6
Configuration Selection: Selects which potentiometer will be programmed. 00 = Potentiometer 0 will be programmed. 01 = Potentiometer 1 will be programmed. These bits determine the wiper setting of the selected potentiometer. Available wiper settings are determined by the attenuation option as described in the Configuration Register section.
bits 5-0
10
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Dual NV Audio Taper Digital Potentiometer
Configuration Register If 10 is entered as the value of the two MSBs of the Command Byte, then the Configuration Register is to be modified. The three LSBs of the Configuration Register control the NV/volatile wiper setting, the zerocrossing detection feature, and the potentiometer attenuation configuration.
DS1881
CONFIGURATION REGISTER
Factory Default: Memory Type: 87h NV (EEPROM)
1 b7
0 b6
X b5
X b4
X b3
V/NV CONTROL b2
ZEROCROSSING b1
POT CONFIG b0
bits 7, 6 bits 5, 4, 3
Configuration Selection: When bit 7 is set to a 1 and bit 6 is set to a 0, the following configuration bits can be set and stored in EEPROM. These bits have no function. Volatile/Nonvolatile Potentiometer Register Control Bit: A control bit that sets the potentiometer registers to be either volatile or nonvolatile memory. 0 = Potentiometer registers are set to nonvolatile memory storage. 1 = Potentiometer registers are set to volatile memory storage. On power-up, the potentiometer wipers are in the mute position (default). Zero-Crossing Detection Enable Bit: A bit used to enable and disable the zero-crossing functionality. 0 = Zero-crossing detection is disabled. 1 = Zero-crossing detection is enabled (default). Potentiometer Position Configuration: A control bit used to select the number of positions both potentiometers have. 0 = Potentiometers have 63 positions and mute. 1 = Potentiometers have 33 positions and mute (default).
bit 2
bit 1
bit 0
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Dual NV Audio Taper Digital Potentiometer DS1881
I2C Interface for the DS1881
The CE pin serves as a communication enable pin. When active (CE = 0), the inputs SDA and SCL are recognized by the device. If inactive (CE = 1), pins SDA and SCL are disabled, making I 2 C communication impossible. Three pins, A0, A1, A2, serve as slave address inputs. For multidrop configurations, they allow eight such devices to be addressed by the same I2C bus. If the I2C address matches the hardware levels of these bits, the DS1881 is allowed to receive communications from the I2C bus. The I2C slave address byte is shown below. This is the first byte transmitted from the master to the DS1881. The upper nibble value is fixed to 0101. Bit values A2, A1, and A0 are determined by the states of the corresponding pins. The LSB, R/W, determines whether a read or write will be performed. The next byte to be transmitted is the Command Byte (see the Command Byte section for details).
SLAVE ADDRESS BYTE 0 MSB 1 0 1 A2 A1 A0 R/W LSB
Reading Pot Values
As shown in Figure 1, the DS1881 provides one read command operation. This operation allows the user to read both Potentiometer Wiper Setting Registers and the Configuration Register. To initiate a read operation, the R/W bit of the slave address byte is set to 1. Communication to read the DS1881 begins with a START condition, which is issued by the master device. The slave address byte sent from the master device follows the START condition. Once a matching slave address byte has been received by the DS1881, the DS1881 responds with an acknowledge. The master can then begin to receive data. The value of the wiper
of Potentiometer 0 is the first returned from the DS1881. It is then followed by the value of Potentiometer 1 and then the value of the Configuration Register. Once the 8 bits of the Configuration Register have been sent, the master needs to issue an acknowledge, unless it is the last byte to be read, in which case the master issues a not acknowledge. If desired, the master may stop the communication transfer at this point by issuing the STOP condition after the not acknowledge. However, if the value of the three registers is needed again, the transfer can continue by clocking the 8 bits of the Potentiometer 0 value as described above.
READ PROTOCOL SLAVE ADDRESS BYTE COMMAND BYTE LSB ACK MSB 0 0 POT-0 LSB ACK MSB 01 POT-1 COMMAND BYTE LSB ACK MSB 10 CONFIG REG COMMAND BYTE LSB STOP ACK
MSB START
0101
AAA 1 210 R/W = 1
DATA BYTES ARE READ IN THE ORDER SHOWN ABOVE.
Figure 1. Read Protocol
12
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Dual NV Audio Taper Digital Potentiometer
Writing Command Byte Values
An example of writing to the DS1881 is shown in Figure 2. The DS1881 has one write command that is used to change the Potentiometer Wiper Setting registers and the Configuration Register. All write operations begin with a START from the master, followed by a slave address byte. The R/W bit should be written to 0, which initiates a write command. Once the slave address byte has been issued and the master receives the acknowledge from the DS1881, potentiometer wiper data is transmitted to the DS1881 by the master device. If the potentiometer has been configured to be written in nonvolatile memory (see the Configuration Register section), then the acknowledge needs to be followed with a STOP command. This command is required from the master at the end of data transmission to initiate the EEPROM write. The STOP command is also accepted if the user has configured the pot values to be written in volatile memory, but no EEPROM is written to.
I2C Definitions
Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See the timing diagram for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See the timing diagram for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTS are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (see Figure 4). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of
DS1881
I2C Serial Interface Descriptions
I2C interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1881 operates as a slave on the I2C bus. Connections to the bus are made by the open-drain I/O lines, SDA and SCL. The following I/O terminals control the I2C serial port: CE, SDA, SCL, A0, A1, and A2. A data transfer protocol and a timing diagram are provided in Figures 3 and 4. The following terminology is commonly used to describe I2C data transfers.
WRITE PROTOCOL SLAVE ADDRESS BYTE COMMAND BYTE LSB ACK MSB 00 POT-0 LSB ACK MSB 01 POT-1 COMMAND BYTE LSB ACK MSB 10 CONFIG REG COMMAND BYTE LSB STOP ACK
MSB START
0101
AAA 0 210 R/W = 0
DATA BYTES CAN BE WRITTEN IN ANY ORDER.
Figure 2. Write Protocol ____________________________________________________________________ 13
Dual NV Audio Taper Digital Potentiometer DS1881
setup time (see Figure 4) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 4) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data.
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 3. Data Transfer Protocol
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 4. I2C Timing Diagram 14 ____________________________________________________________________
Dual NV Audio Taper Digital Potentiometer
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a START condition. The slave address byte (Figure 5) contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1881's slave address is 0101 A2 A1 A0 (binary), where A2, A1, and A0 are the values of the address pins. The address pins allow the device to respond to one of eight possible slave addresses. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master will read data from the slave. If an incorrect slave address is written, the DS1881 will assume the master is communicating with another I2C device and ignore the communications until the next START condition is sent. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the desired number of data bytes and generates a STOP condition. The DS1881 is capable of writing both potentiometer wiper settings and the Configuration Register with a single write transaction. Acknowledge Polling: Any time an EEPROM location is written, the DS1881 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte of data to EEPROM. During the EEPROM write time, the device will not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS1881, which allows the next page to be written as soon as the DS1881 is ready to receive the data. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to write again to the device. EEPROM Write Cycles: When EEPROM writes occur to the memory, the DS1881 will write to all three EEPROM memory locations, even if only a single byte was modified. Because all three bytes are written, the bytes that were not modified during the write transaction are still subject to a write cycle. This can result in all three bytes being worn out over time by writing a single byte repeatedly. The DS1881's EEPROM write cycles are specified in the NV Memory Characteristics table. The specification shown is at the worst-case temperature. If zero-crossing detection is enabled, EEPROM write cycles cannot begin until after the zero-crossing detection is complete. Reading a Single Byte from a Slave: To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. When a single byte is read, it will always be the Potentiometer 0 value. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it NACKs to indicate the end of the transfer and generates a STOP condition. The first byte read will be the Potentiometer 0 Wiper Setting. The next byte will be the Potentiometer 1 Wiper Setting. The third byte is the Configuration Register byte. If an ACK is issued by the master following the Configuration Register byte, then the DS1881 will send the Potentiometer 0 Wiper Setting again. This round robin reading will occur as long as each byte read is followed by an ACK from the master.
15
DS1881
I2C Communication
Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the byte of data, and generate a STOP condition. The master must read the slave's acknowledgement during all byte write operations.
DETERMINES READ OR WRITE FUNCTION
7-BIT SLAVE ADDRESS
0 MSB
1
0
1
A2
A1
A0
R/W LSB
A2, A1, AND A0 PIN VALUES
Figure 5. DS1881's Slave Address Byte
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Dual NV Audio Taper Digital Potentiometer DS1881
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power supplies are decoupled with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the voltage supplies and GND pins to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS1881 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be utilized for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics table are within specification.
Typical Operating Circuit
5V (VDD) VDD 4.7k 4.7k DECOUPLING CAPACITOR GND SDA HOST C SCL CE VCC 5V (VCC)
DECOUPLING CAPACITOR
DS1881
H1 W1
A2 A1 A0
L1 AUDIO OUT H0 W0 L0
5V (VCC) 20k AUDIO IN (AC + VCC / 2) VCC / 2 = 2.5V 20k
Chip Topology
TRANSISTOR COUNT: 52,353 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney

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